DAC1205D650 Datasheet, PDF (20/42 Pages) NXP Semiconductors – Dual 12-bit DAC, up to 650 Msps; 2´ 4´ and 8´ interpolating

NXP Semiconductors
DAC1205D650
Dual 12-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
DAC1205D650_1
Product data sheet
Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit Symbol
Access Value Description
7
DAC_B_PD
R/W
DAC B power
0
on
1
off
6
DAC_B_SLEEP
R/W
DAC B Sleep mode
0
disabled
1
enabled
5 to 1 DAC_B_OFFSET[4:0]
R/W
lower 5 bits for the DAC B offset
Table 23. DAC_B_Cfg_2 register (address 0Dh) bit description
Bit Symbol
Access Value Description
7 to 6 DAC_B_GAIN_COARSE[1:0] R/W -
less significant 2 bits for the DAC B gain
setting for coarse adjustment
5 to 0 DAC_B_GAIN_FINE[5:0]
R/W -
the 6 bits for the DAC B gain setting for
fine adjustment
Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description
Bit Symbol
Access Value Description
7 to 6 DAC_B_GAIN_COARSE[3:2] R/W -
most significant 2 bits for the DAC B gain
setting for coarse adjustment
5 to 0 DAC_B_OFFSET[10:5]
R/W -
most significant 6 bits for the DAC B
offset
Table 25. DAC_Cfg register (address 0Fh) bit description
Default settings are shown highlighted.
Bit Symbol
Access Value Description
1
MINUS_3DB
R/W
NCO gain
0
unity
1
−3 dB
0
NOISE_SHPER
R/W
noise shaper
0
disabled
1
enabled
Table 26. DAC_A_Aux_MSB register (address 1Ah) bit description
Bit Symbol
Access Value Description
7 to 0 AUX_A[9:2]
R/W -
most significant 8 bits for the auxiliary DAC A
Table 27. DAC_A_Aux_LSB register (address 1Bh) bit description
Default settings are shown highlighted.
Bit
Symbol
Access Value Description
7
AUX_A_PD
R/W
auxiliary DAC A power
0
on
1
off
1 to 0 AUX_A[1:0]
R/W
lower 2 bits for the auxiliary DAC A
Rev. 01 — 28 July 2009
© NXP B.V. 2009. All rights reserved.
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