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| 74HC193_13 Datasheet, PDF (20/30 Pages) NXP Semiconductors – Presettable synchronous 4-bit binary up/down counter | |||
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NXP Semiconductors
74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
VI
Dn input
GND
VI
PL input
GND
VOH
Qn output
VOL
VM
tsu
th
VM
tsu
th
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The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 10.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. The data input (Dn) to parallel load input (PL) set-up and hold times
VI
PL, MR, Dn
input
GND
VOH
TCU, TCD
output
VOL
tPLH
VM
VM
tPHL
001aag418
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 14. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs
(TCU, TCD) propagation delays
VI
CPU or CPD
input
GND
VI
CPD or CPU
input
GND
VM
th
VM
Measurement points are given in Table 10.
Fig 15. The CPU to CPD or CPD to CPU hold times
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74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 â 24 June 2013
© NXP B.V. 2013. All rights reserved.
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