PRTR5V0U2F_09 Datasheet, PDF (2/12 Pages) NXP Semiconductors – Ultra low capacitance double rail-to-rail ESD protection

NXP Semiconductors
PRTR5V0U2F; PRTR5V0U2K
Ultra low capacitance double rail-to-rail ESD protection
1.4 Quick reference data
Table 2. Quick reference data
T_amb = 25 °C unless otherwise specified.
Symbol Parameter
Per channel
C_(I/O-GND)
input/output to ground
capacitance
C_(I/O-I/O)
input/output to input/output
capacitance
Zener diode
V_RWM
C_sup
reverse standoff voltage
supply pin to ground
capacitance
[1] Measured from pin 1, 3, 4 or 6 to ground.
[2] Measured from pin 1 or 6 to pin 3 or 4.
[3] Measured from pin 5 to ground.
Conditions
f = 1 MHz;
V_(I/O-GND) = 0 V
f = 1 MHz;
V_(I/O-I/O) = 0 V
f = 1 MHz;
V_CC = 0 V
2. Pinning information
Min Typ Max Unit
[1] _-
1.0 1.5 pF
[2] _-
0.6 -
pF
[3] _-
[3] _-
-
5.5 V
16 -
pF
Table 3. Pinning
Pin Symbol
Description
PRTR5V0U2F (SOT886)
1
I/O1
input/output 1
2
GND
ground
3
I/O2
input/output 2
4
I/O2
input/output 2
5
V_CC
6
I/O1
supply voltage
input/output 1
PRTR5V0U2K (SOT891)
1
I/O1
input/output 1
2
GND
ground
3
I/O2
input/output 2
4
I/O2
input/output 2
5
V_CC
6
I/O1
supply voltage
input/output 1
Simplified outline
Graphic symbol
1
2
3
6
5
4
bottom view
1
6
2
5
3
4
006aab349
123
654
bottom view
1
6
2
5
3
4
006aab349
PRTR5V0U2F_PRTR5V0U2K_2
Product data sheet
Rev. 02 — 19 February 2009
© NXP B.V. 2009. All rights reserved.
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