PCA9505 Datasheet, PDF (2/31 Pages) NXP Semiconductors – 40-bit I2C-bus I/O port with RESET, OE and INT

NXP Semiconductors
PCA9505/06
40-bit I²C-bus I/O port with RESET, OE and INT
I Inputs:
N Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change
N Polarity Inversion register allows inversion of the polarity of the I/O pins when read
I Active LOW reset (RESET) input pin resets device to power-up default state
I 3 programmable address pins allowing 8 devices on the same bus
I Designed for live insertion
N Minimize line disturbance (I_OFF and power-up 3-state)
N Signal transient rejection (50 ns noise filter and robust I²C-bus state machine)
I Low standby current
I −40 °C to +85 °C operation
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA
I Offered in TSSOP56 (PCA9505, PCA9506) and HVQFN56 (PCA9506) packages
3. Applications
I Servers
I RAID systems
I Industrial control
I Medical equipment
I PLCs
I Cell phones
I Gaming machines
I Instrumentation and test measurement
4. Ordering information
Table 1. Ordering information
Type number Topside mark
PCA9505DGG PCA9505DGG
Package
Name
TSSOP56
PCA9506DGG PCA9506DGG TSSOP56
PCA9506BS
PCA9506BS
HVQFN56
Description
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
plastic thermal enhanced very thin quad flat package;
no leads; 56 terminals; body 8 × 8 × 0.85 mm
Version
SOT364-1
SOT364-1
SOT684-1
PCA9505_9506_3
Product data sheet
Rev. 03 — 6 June 2007
© NXP B.V. 2007. All rights reserved.
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