GTL2000 Datasheet, PDF (2/2 Pages) NXP Semiconductors – 22-bit GTL processor voltage clamp

application that requires uni- or
bidirectional voltage translation for
voltage levels between 1 and 5 V.
The open-drain construction, which
eliminates the need for directional
control, makes the translators ideal for
designs that combine low-voltage (1.0 to
1.8 V) and legacy (3.3 and/or 5.5 V) I²C-
bus signals. The translators can change
I²C-bus signal levels at speeds up to 3.4
MHz.
The translators can also be used in
designs that combine GTL and LVTTL/
TTL signals, shifting processor sideband
I/O signals between voltage levels.
Bidirectional voltage translation
To configure the translators for
bidirectional clamping, the G_REF input
must be connected to D_REF and both
pins must be pulled to the high-side
V_CC through a pull-up resistor (typically
200 kΩ). A filter capacitor on D_REF is
recommended.
The CPU output can be set as totem
pole or open drain (pull-up resistors may
be required), as can the chipset output
(pull-up resistors are required to pull
the Dn outputs to V_CC). No directional
control is needed if both outputs are set
as open drain. If either output is set to
totem pole, however, there may be high-
to-low contentions in either direction. To
prevent this, set data as unidirectional
or use 3-stateable outputs with a
mechanism for direction control.
The opposite side of S_REF is connected
to the CPU power-supply voltage. When
D_REF is connected through a 200-kΩ
resistor to V_CC and S_REF is set between 1.0
and V_CC minus 1.5 V, the output of each
Sn has a maximum output voltage equal
to S_REF and the output of each Dn has a
maximum output voltage equal to the
voltage of the pull-up resistor (3.3 and/or
5 V).
Unidirectional voltage translation
The same configuration can be used for
one-way voltage translation, either up
or down. For down-only translation, if
the chipset I/O are open drain, pull-up
resistors are required.
For up-only translation, a pull-up resistor
is required on the high-side voltage (Dn).
This is because the translator will only
pass the reference source voltage (S_REF)
as a high when doing up-translation. The
driver on the low-side voltage only needs
a pull-up resistor if it is set as open drain.
For more information on using the
GTL20xx family, please refer to
Application Note AN10145 at www.nxp.
com/interface.
GND 1
SREF 2
S1 3
S2 4
S3 5
S4 6
S5 7
S6 8
S7 9
S8 10
S9 11
S10 12
S11 13
S12 14
S13 15
S14 16
S15 17
S16 18
S17 19
S18 20
S19 21
S20 22
S21 23
S22 24
48 GREF
47 DREF
GTL2002
46 D1
45 D2
44 D3
43 D4
GTL2003
42 D5
41 D6
GTL2010
40 D7
39 D8
38 D9
37 D10
36 D11
35 D12
34 D13
33 D14
32 D15
31 D16
30 D17
29 D18
28 D19
27 D20
26 D21
25 D22
1.8 V
1.5 V
1.2 V
1.0 V
VCORE
CPU I/O
GTL2002
GND GREF
SREF DREF
S1
D1
S2
D2
200 K7
Increase bit size by using
8-bit GTL2003 or 10-bit
GTL2010 or 22-bit GTL2000
S3
D3
S4
D4
S5
D5
Sn
Dn
5V
Totem Pole or
Open Drain I/O
VCC
Chipset I/O
3.3 V
VCC
Chipset I/O
GTL20xx pinout diagram
Typical configuration for bidirectional voltage translation
Ordering information
Package
SO
SSOP
TSSOP
HVQFN
DHVQFN
VSSOP
XQFN
Container
Tube
T&R
Tube
T&R
Tube
T&R
T&R
T&R
T&R
T&R
GTL2000
--
--
GTL2000DL
GTL2000DL-T
GTL2000DGG
GTL2000DGG-T
--
--
--
--
GTL2002
GTL2002D
GTL2002D-T
--
--
--
GTL2002DP-T
--
--
GTL2002DC-T
GTL2002GM-T
GTL2003
--
--
--
--
GTL2003PW
GTL2003PW-T
--
GTL2003BQ-T
--
--
GTL2010
--
--
--
--
GTL2010PW
GTL2010PW-T
GTL2010BS-T
--
--
--
Note: In Europe and Asia, for tube orders, add “, 112” (e.g. GTL2010PW, 112), and for tape and
reel orders, replace “-T” with “, 118” (e.g. GTL2010PW, 118).
www.nxp.com
© 2007 NXP N.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and
may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof
does not convey nor imply any license under patent or other industrial or intellectual property rights.
Date of release: March 2007
Document order number: 9397 750 15911
Printed in the USA