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74LVC1G125GW165 Datasheet, PDF (2/20 Pages) NXP Semiconductors – Bus buffer/line driver; 3-state
NXP Semiconductors
74LVC1G125
Bus buffer/line driver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name Description
Version
74LVC1G125GW
40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; SOT353-1
body width 1.25 mm
74LVC1G125GV
40 C to +125 C SC-74A plastic surface-mounted package; 5 leads
SOT753
74LVC1G125GM
40 C to +125 C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1  1.45  0.5 mm
SOT886
74LVC1G125GF
40 C to +125 C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1  1  0.5 mm
SOT891
74LVC1G125GN
40 C to +125 C
XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9  1.0  0.35 mm
SOT1115
74LVC1G125GS
40 C to +125 C
XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0  1.0  0.35 mm
SOT1202
74LVC1G125GX
40 C to +125 C
X2SON5 X2SON5: plastic thermal enhanced extremely thin SOT1226
small outline package; no leads; 5 terminals;
body 0.8  0.8  0.35 mm
4. Marking
Table 2. Marking
Type number
74LVC1G125GW
74LVC1G125GV
74LVC1G125GM
74LVC1G125GF
74LVC1G125GN
74LVC1G125GS
74LVC1G125GX
Marking code[1]
VM
V25
VM
VM
VM
VM
VM
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
2A
Y4
1 OE
mna118
Fig 1. Logic symbol
2
4
1
EN
mna119
Fig 2. IEC logic symbol
A
Y
OE
Fig 3. Logic diagram
mna120
74LVC1G125
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 2 July 2012
© NXP B.V. 2012. All rights reserved.
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