74HC4316PW-T Datasheet, PDF (2/15 Pages) NXP Semiconductors – Quad bilateral switches

Philips Semiconductors
Quad bilateral switches
Product specification
74HC/HCT4316
FEATURES
• Low “ON” resistance:
160 Ω (typ.) at V_CC − V_EE = 4.5 V
120 Ω (typ.) at V_CC − V_EE = 6.0 V
80 Ω (typ.) at V_CC − V_EE = 9.0 V
• Logic level translation:
to enable 5 V logic to communicate
with ± 5 V analog signals
• Typical “break before make” built in
• Output capability: non-standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4316 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4316 have four independent analog
switches. Each switch has two input/output terminals
(nY, nZ) and an active HIGH select input (nS). When the
enable input (E) is HIGH, all four analog switches are
turned off.
Current through a switch will not cause additional V_CC
current provided the voltage at the terminals of the switch
is maintained within the supply voltage range;
V_CC >> (V_Y, V_Z) >> V_EE. Inputs nY and nZ are electrically
equivalent terminals.
V_CC and GND are the supply voltage pins for the digital
control inputs (E and nS). The V_CC to GND ranges are 2.0
to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (nY and nZ) can swing between
V_CC as a positive limit and V_EE as a negative limit.
V_CC − V_EE may not exceed 10.0 V.
See the “4016” for the version without logic level
translation.
QUICK REFERENCE DATA
V_EE = GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
t_PZH
t_PZL
t_PHZ/ t_PLZ
C_I
C_PD
C_S
turn “ON” time
E to V_OS
nS to V_OS
turn “ON” time
E to V_OS
nS to V_OS
turn “OFF” time
E to V_OS
nS to V_OS
input capacitance
power dissipation capacitance per switch
max. switch capacitance
CONDITIONS
TYPICAL
HC
HCT
C_L = 15 pF; R_L = 1 kΩ;
V_CC = 5 V
19
19
16
17
19
24
16
21
notes 1 and 2
20
21
16
19
3.5
3.5
13
14
5
5
UNIT
ns
ns
ns
ns
ns
ns
pF
pF
pF
Notes
1. C_PD is used to determine the dynamic power
dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ { (C_L + C_S) × V_CC2 × f_o }
where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ { (C_L + C_S) × V_CC2 × f_o } = sum of outputs
C_L = output load capacitance in pF
C_S = max. switch capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
September 1993
2