PCF8534A_15 Datasheet, PDF (19/52 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates

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drive mode
LCD segments
LCD backplanes
static
S_n+2
S_n+3
S_n+4
S_n+5
S_n+6
a
b
f
g
e
c
d
S_n+1 ^BP0
S_n
S_n+7
DP
rows
n
display RAM _{0 c}
rows/backplane
outputs (BP)
1
x
2x
3x
display RAM filling order
columns
display RAM address/segment outputs (s)
byte1
n+1 n+2 n+3 n+4 n+5 n+6
b
a
f
g
e
d
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
n+7
DP
x
x
x
transmitted display byte
MSB
LSB
c b a f g e d DP
1:2
multiplex
S_n
a
b
S_n+1 f
g
S_n+2 e
c
S_n+3
d
BP0
DP
columns
display RAM address/segment outputs (s)
byte1
byte2
rows
n
display RAM _{0 a}
rows/backplane
BP1 _{outputs (BP)} 1 b
2x
3x
n+1 n+2 n+3
f
e
d
g
c
DP
x
x
x
x
x
x
MSB
LSB
a b f g e c d DP
1:3
multiplex
S_n+1
a
S_{n+2 f}
b _Sn
BP0
g
e
c
d
BP1
DP
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
rows
n n+1 n+2
display RAM _{0 b a}
f
rows/backplane
BP2 _{outputs (BP)} ^{1 DP d}
e
2c g
x
3x x
x
MSB
LSB
b DP c a d g f e
1:4
multiplex
S_n
a
b
f
g
e
c
S_n+1
d
BP0
BP1
DP
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
byte4
byte5
BP2
rows
n
display RAM _{0 a}
BP3
rows/backplane
outputs (BP)
1
2
c
b
3 DP
n+1
f
e
g
d
MSB
LSB
a c b DP f e g d
x = data bit unchanged.
Fig 13. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I²C-bus
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