PCA9505_10 Datasheet, PDF (18/34 Pages) NXP Semiconductors – 40-bit I2C-bus I/O port with RESET, OE and INT

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slave address
command register
repeated START condition
slave address
At this moment master-transmitter becomes master-receiver,
and slave-receiver becomes slave-transmitter.
SDA S 0 1 0 0 A2 A1 A0 0 A 1 0 D5 D4 D3 D2 D1 D0 A Sr 0 1 0 0 A2 A1 A0 1 A
(cont.)
START condition
R/W AI = 1
acknowledge from slave
R/W acknowledge from slave
acknowledge
from slave
D[5:0] = 00 0000 for Input Port register bank 0
D[5:0] = 00 1000 for Output Port register bank 0
D[5:0] = 01 0000 for Polarity Inversion register bank 0
D[5:0] = 01 1000 for Configuration register bank 0
D[5:0] = 10 0000 for Mask Interrupt register bank 0
acknowledge from master acknowledge from master
no acknowledge from master
data from register
data from register
data from register
DATA
A
DATA
A
DATA
AP
first byte
register determined by D[5:0]
second byte
last byte
STOP
condition
002aab499
If AI = 0, the same register is read during the whole sequence.
If AI = 1, the register value is incremented after each read. When the last register bank is read, it rolls over to the first byte of the category (see category definition in
Section 7.2 “Command register”).
The INT signal is released only when the last register containing an input that changed has been read. For example, when IO2_4 and IO4_7 change at the same time and
an Input Port register’s read sequence is initiated, starting with IP0, INT is released after IP4 is read (and not after IP2 is read).
Fig 14. Read from Input Port, Output Port, I/O Configuration, Polarity Inversion or Mask Interrupt registers