PCA8565 Datasheet, PDF (18/39 Pages) NXP Semiconductors – Real time clock/calender

NXP Semiconductors
PCA8565
Real time clock/calendar
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a
minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is
divided down to 1 Hz by a 2⁶ divide chain called a pre-scaler. The pre-scaler can be set
into a known state by using bit STOP. When bit STOP is set, the pre-scaler is reset to 0
(STOP must be cleared before the pre-scaler can operate again).
From a STOP condition, the first 1 second increment will take place after 32 positive
edges on CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment.
Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.
When entering the test mode, no assumption as to the state of the pre-scaler can be
made.
Operation example:
1. Set EXT_CLK test mode (Control_1, bit TEST1 = 1).
2. Set STOP (Control_1, bit STOP = 1).
3. Clear STOP (Control_1, bit STOP = 0).
4. Set time registers to desired value.
5. Apply 32 clock pulses to CLKOUT.
6. Read time registers to see the first change.
7. Apply 64 clock pulses to CLKOUT.
8. Read time registers to see the second change.
Repeat 7 and 8 for additional increments.
9.12 STOP bit function
The function of the STOP bit is to allow for accurate starting of the time circuits. The STOP
bit function will cause the upper part of the prescaler (F₂ to F₁₄) to be held in reset and
thus no 1 Hz ticks will be generated (see Figure 10). The time circuits can then be set and
will not increment until the STOP bit is released (see Figure 11 and Table 28).
OSC STOP
DETECTOR
reset
OSC
Fig 10. STOP bit
F₀
F₁
F₂
RES
F₁₃
RES
F₁₄
RES
1 Hz tick
stop
1 Hz
32 Hz
1024 Hz
32768 Hz
CLKOUT source
013aaa089
PCA8565_2
Product data sheet
Rev. 02 — 16 June 2009
© NXP B.V. 2009. All rights reserved.
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