P89LPC9201 Datasheet, PDF (17/74 Pages) NXP Semiconductors – 8-bit microcontroller with accelerated two-clock 80C51 core 2 kB/4 kB/8 kB 3 V byte-erasable flash with 8-bit ADC

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Table 4. Special function registers - P89LPC9201/9211/922A1
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr. _MSB
LSB
Reset value
Hex Binary
Bit address 8F
8E
8D
8C
8B
8A
89
88
TCON*
Timer 0 and 1 88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0 00
0000 0000
control
TH0
Timer 0 high 8CH
00
0000 0000
TH1
Timer 1 high 8DH
00
0000 0000
TL0
Timer 0 low
8AH
00
0000 0000
TL1
Timer 1 low
8BH
00
0000 0000
TMOD
Timer 0 and 1 89H T1GATE
mode
T1C/T
T1M1
T1M0 T0GATE T0C/T
T0M1
T0M0 00
0000 0000
TRIM
Internal
96H RCCLK
oscillator trim
register
ENCLK
TRIM.5
TRIM.4
TRIM.3
TRIM.2
TRIM.1
TRIM.0 ^[5][6]
WDCON Watchdog
A7H PRE2
PRE1
PRE0
-
control register
-
WDRUN WDTOF WDCLK ^[4][6]
WDL
Watchdog load C1H
FF
1111 1111
WFEED1
Watchdog
feed 1
C2H
WFEED2
Watchdog
feed 2
C3H
[1] All ports are in input only (high-impedance) state after power-up.
[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3] The RSTSRC register reflects the cause of the P89LPC9201/9211/922A1 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF;
the power-on reset value is x011 0000.
[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.