ADC1210S Datasheet, PDF (17/36 Pages) NXP Semiconductors – Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs

NXP Semiconductors
ADC1210S series
ADC1210S series; CMOS or LVDS DDR digital outputs
Figure 13 to Figure 16 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
VREF
330 pF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
005aaa116
Fig 13. Internal reference, 2 V (p-p) full-scale
VREF
330
pF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
005aaa117
Fig 14. Internal reference, 1 V (p-p) full-scale
VREF
V
0.1 μF
REFERENCE
EQUIVALENT
SCHEMATIC
SENSE
VREF
330 pF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
VDDA
005aaa119
Fig 15. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
005aaa118
Fig 16. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
11.3.2 Reference gain control
The reference gain is programmable between 0 dB to −6 dB in 1 dB steps via the SPI
(see Table 22). The corresponding full-scale input voltage range varies between 2 V (p-p)
and 1 V (p-p), as shown in Table 13:
Table 13. Reference SPI gain control
INTREF[2:0]
Gain (dB)
000
0 dB
001
−1 dB
010
−2 dB
011
−3 dB
100
−4 dB
101
−5 dB
110
−6 dB
111
reserved
Full-scale (V (p-p))
2V
1.78 V
1.59 V
1.42 V
1.26 V
1.12 V
1V
x
ADC1210S_SER_1
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 9 April 2010
© NXP B.V. 2010. All rights reserved.
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