 English |
|
|
|
|
|
|
|
| PCA2003_09 Datasheet, PDF (16/21 Pages) NXP Semiconductors – 32 kHz watch circuit with programmable adaptive motor pulse and pulse period | |||
| |||
| ◁ |
NXP Semiconductors
PCA2003
32 kHz watch circuit with programmable adaptive motor pulse
9. Characteristics
Table 10. Characteristics
VDD = 1.55 V; VSS = 0 V; fosc = 32.768 kHz; Tamb = 25 °C; quartz crystal: RS = 40 kâ¦, C1 = 2 fF to 3 fF, CL = 8.2 pF; unless
otherwise speciï¬ed.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply
VDD
supply voltage
normal operating mode;
Tamb = â10 °C to +60 °C
âVDD
supply voltage variation âV/ât = 1 V/µs
IDD
supply current
between motor pulses
between motor pulses
at VDD = 3.5 V
Tamb = â10 °C to +60 °C
stop mode;
pad RESET connected to
VDD
Motor output
1.1
1.55
3.60
V
-
-
0.25
V
-
90
120
nA
-
120
180
nA
-
-
200
nA
-
100
135
nA
Vsat
saturation voltage
Rmotor = 2 kâ¦;
[1] -
Tamb = â10 °C to +60 °C
Zo(sc)
output impedance
between motor pulses;
-
(short circuit)
Imotor < 1 mA
Oscillator
150
200
mV
200
300
â¦
Vstart
gm
tstartup
âf/f
CL(itg)
start voltage
transconductance
start-up time
frequency stability
integrated load
capacitance
Vi(osc) ⤠50 mV (p-p)
âVDD = 100 mV
1.1
-
-
V
5
10
-
µS
-
0.3
0.9
s
-
0.05
0.20
ppm
4.3
5.2
6.3
pF
Rpar
parasitic resistance allowed resistance between
20
-
-
Mâ¦
adjacent pads
Pad RESET
fo
output frequency
-
32
-
Hz
VO(dif)
differential output
RL = 1 Mâ¦; CL = 10 pF
[2] 1.4
-
-
V
voltage
tr
rise time
RL = 1 Mâ¦; CL = 10 pF
[2] -
tf
fall time
RL = 1 Mâ¦; CL = 10 pF
[2] -
Ii(AV)
average input current pad RESET connected to
-
VDD or VSS
1
-
µs
1
-
µs
10
20
nA
[1] P1 + ... + P4 + N1 + N2 (see Section 7.2).
[2] RL and CL are a load resistor and load capacitor, externally connected to pad RESET.
PCA2003_2
Product data sheet
Rev. 02 â 21 July 2009
© NXP B.V. 2009. All rights reserved.
16 of 21
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese