PCA85176 Datasheet, PDF (15/44 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates

NXP Semiconductors
PCA85176
Universal LCD driver for low multiplex rates
7.10 Display RAM
The display RAM is a static 40 × 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map, Figure 10, shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,
and BP3 respectively.
display RAM addresses (columns)/segment outputs (S)
01234
35 36 37 38 39
0
display RAM bits
(rows)/
1
backplane outputs
(BP)
2
3
mbe525
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs; and between the bits in a RAM row and the backplane outputs.
Fig 10. Display RAM bit map
When display data is transmitted to the PCA85176 the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for an acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triples or
quadruples. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in Figure 11; the RAM filling organization depicted
applies equally to other LCD types.
PCA85176_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 14 April 2010
© NXP B.V. 2010. All rights reserved.
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