PCA6408A Datasheet, PDF(15/40 Page) NXP Semiconductors – Low-voltage, 8-bit I2C-bus and SMBus I/O expander with interrupt output, reset, and configuration registers

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PCA6408A Datasheet, PDF (15/40 Pages) NXP Semiconductors – Low-voltage, 8-bit I2C-bus and SMBus I/O expander with interrupt output, reset, and configuration registers

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NXP Semiconductors

PCA6408A

Low-voltage, 8-bit I2C-bus and SMBus I/O expander

Table 11. Recommended supply sequencing and ramp rates

Tamb = 25 ï°C (unless otherwise noted). Not tested; specified by design.

Symbol Parameter

Condition

Min Typ Max Unit

(dV/dt)f fall rate of change of voltage

Figure 15

0.1 -

(dV/dt)r rise rate of change of voltage

Figure 15

0.1 -

td(rst)

reset delay time

Figure 15; re-ramp time when

VDD(P) drops to VSS

Figure 16; re-ramp time when

VDD(P) drops to VPOR(min) ï 50 mV

ïVDD(gl) glitch supply voltage difference

Figure 17

[1] -

tw(gl)VDD supply voltage glitch pulse width Figure 17

[2] -

VPOR(trip) power-on reset trip voltage

falling VDD(P)

0.7 -

rising VDD(P)

2000 ms

ïs

1.0 V

ïs

1.4 V

[1] Level that VDD(P) can glitch down to with a ramp rate of 0.4 ïs/V, but not cause a functional disruption when tw(gl)VDD < 1 ïs.

[2] Glitch width that will not cause a functional disruption when ïVDD(gl) = 0.5 ï´ VDD(P).

Glitches in the power supply can also affect the power-on reset performance of this

device. The glitch width (tw(gl)VDD) and glitch height (ïVDD(gl)) are dependent on each

other. The bypass capacitance, source impedance, and device impedance are factors that

affect power-on reset performance. Figure 17 and Table 11 provide more information on

how to measure these specifications.

VDD(P)

âVDD(gl)

tw(gl)VDD

time

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Fig 17. Glitch width and glitch height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition

is released and all the registers and the I2C-bus/SMBus state machine are initialized to

their default states. The value of VPOR differs based on the VDD(P) being lowered to or from

0 V. Figure 18 and Table 11 provide more details on this specification.

VDD(P)

VPOR (rising VDD(P))

VPOR (falling VDD(P))

POR

time

PCA6408A

Product data sheet

Fig 18. Power-on reset voltage (VPOR)

All information provided in this document is subject to legal disclaimers.

Rev. 1 â 27 September 2012

time

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