74HC4017 Datasheet, PDF (15/23 Pages) NXP Semiconductors – Johnson decade counter with 10 decoded outputs

NXP Semiconductors
74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs
CP0 ^MR
74HC4017
74HCT4017
CP1
Q0 Q1^{- - - -} Q8 Q9
CP0 ^MR
74HC4017
74HCT4017
CP1
Q0 Q1^{- - - -} Q8 Q9
CP0 ^MR
74HC4017
74HCT4017
CP1
Q1 ^{- - - - - -} Q8 Q9
9 decoded
outputs
8 decoded
outputs
8 decoded
outputs
clock
first stage
intermediate stages
last stage
001aah248
Fig 12. Counter expansion
Remark: It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0
when CP1 is LOW, as this would cause an extra count.
Figure 13 shows an example of a divide-by 2 through divide-by 10 circuit using one
74HC4017; 74HCT4017. Since the 74HC4017; 74HCT4017 has an asynchronous reset,
the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output
pulse widths can be enlarged by inserting an RC network at the MR input.
divide - by 5
divide - by 2
divide - by 6
divide - by 7
divide - by 3
74HC4017
74HCT4017
Q5
Q1
Q0
Q2
Q6
Q7
Q3
GND
V_CC
MR
CP0
CP1
Q5-9
Q9
Q4
Q8
Fig 13. Divide-by 2 through divide-by 10
V_CC
fin
divide - by 10
divide - by 9
divide - by 4
divide - by 8
fout
001aah249
74HC_HCT4017_3
Product data sheet
Rev. 03 — 8 January 2008
© NXP B.V. 2008. All rights reserved.
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