SSTUG32865 Datasheet, PDF (14/28 Pages) NXP Semiconductors – 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-1G RDIMM applications

NXP Semiconductors
SSTUG32865
1.8 V DDR2-1G registered buffer with parity
Dn ²²
22
DQ
QnA
QnB
D
PARIN
D
D
LATCHING AND
RESET FUNCTION⁽¹⁾
PTYERR
CLOCK
002aaa417
(1) This function holds the error for two cycles. For details, see Section 7 “Functional description” and Figure 4 “RESET
switches from LOW to HIGH”.
Fig 7. Parity logic diagram
SSTUG32865_1
Product data sheet
Rev. 01 — 16 August 2007
© NXP B.V. 2007. All rights reserved.
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