PCA9555 Datasheet, PDF (14/34 Pages) NXP Semiconductors – 16-bit I2C and SMBus I/O port with interrupt

NXP Semiconductors
PCA9555
16-bit I²C-bus and SMBus I/O port with interrupt
6.5.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins changes state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read (see Figure 13). A pin configured as an
output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt
caused by Port 0 will not be cleared by a read of Port 1 or the other way around.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
7. Characteristics of the I²C-bus
The I²C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
SDA
SCL
Fig 15. Bit transfer
data line
stable;
data valid
change
of data
allowed
mba607
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 16).
PCA9555_8
Product data sheet
SDA
SCL
S
START condition
Fig 16. Definition of START and STOP conditions
Rev. 08 — 22 October 2009
P
STOP condition
mba608
© NXP B.V. 2009. All rights reserved.
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