AN10897 Datasheet, PDF (14/30 Pages) NXP Semiconductors – A guide to designing for ESD and EMC

NXP Semiconductors
AN10897
A guide to designing for ESD and EMC
3. A practical approach to schematic and PCB design
Electromagnetic compatibility and ESD immunity must be considered in the early design
stage of a system. If ignored, problems encountered later in testing or in the field will
become very difficult and expensive to fix.
A crucial element in EMC/ESD immunity is a solid PCB design. Good practices such as
decoupling power and I/O lines to ground, voltage and frequency (bandwidth) limiting,
wave shaping (edge-rate control), using negative feedback, refresh cycling, WDT, and
fault tolerant software—all play collectively an important role in improving EMC and ESD
immunity.
3.1 Board structure - functional grouping
A PCB board should be divided by functional groups: analog, digital, power supply,
high noise, and IO groups. Figure 15 shows the sample placement of each group.
DIGITAL
NOISY
POWER
SUPPLY
IO
ANALOG
002aae802
Fig 15. Sample placement of functional groups
In the schematic, each component should have a reference designator identifying the
group to which it belongs. This will provide the layout engineer with the necessary
information for the correct placement of components on the board. Traces of a given
group should not cross over to a different group unless it is an interface trace between the
groups.
LOW FREQUENCY
HIGH
FREQUENCY
IO
002aae803
Fig 16. Recommended layout when high frequency signal leave the PCB
AN10897_2
Application note
Rev. 02 — 19 January 2010
© NXP B.V. 2010. All rights reserved.
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