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SSTUG32866 Datasheet, PDF (13/28 Pages) NXP Semiconductors – 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer | |||
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NXP Semiconductors
SSTUG32866
1.8 V DDR2-1G conï¬gurable registered buffer with parity
Table 9. Timing requirements
At recommended operating conditions (see Table 7), unless otherwise speciï¬ed. See Section 11.1.
Symbol Parameter
Conditions
Min Typ
fclock
tW
tACT
tINACT
tsu
clock frequency
pulse width
CK, CK HIGH or LOW
differential inputs active time
differential inputs inactive time
setup time
DCS before CKâ, CKâ, CSR HIGH;
CSR before CKâ, CKâ, DCS HIGH
-
-
1
-
[1][2] -
-
[1][3] -
-
0.6 -
DCS before CKâ, CKâ, CSR LOW
0.5 -
DODT, DCKE and data (Dn) before CKâ,
CKâ
0.5 -
PAR_IN before CKâ, CKâ
0.5 -
th
hold time
DCS, DODT, DCKE and data (Dn) after
CKâ, CKâ
0.4 -
PAR_IN after CKâ, CKâ
0.4 -
Max Unit
550 MHz
-
ns
10 ns
15 ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
[1] This parameter is not necessarily production tested.
[2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of tACT(max) after RESET is taken
HIGH.
[3] VREF, data and clock inputs must be held at valid levels (not ï¬oating) a minimum time of tINACT(max) after RESET is taken LOW.
Table 10. Switching characteristics
At recommended operating conditions (see Table 7), unless otherwise speciï¬ed. See Section 11.1.
Symbol Parameter
Conditions
Min Typ
fmax
tPDM
maximum input clock frequency
peak propagation delay
single bit switching;
from CKâ and CKâ to Qn
550 -
[1] 1.0
-
tPD
tLH
tHL
tPDMSS
propagation delay
LOW-to-HIGH delay
HIGH-to-LOW delay
simultaneous switching peak
propagation delay
from CKâ and CKâ to PPO
from CKâ and CKâ to QERR
from CKâ and CKâ to QERR
from CKâ and CKâ to Qn
0.5 -
1.2 -
1
-
[1][2] -
-
tPHL
HIGH-to-LOW propagation delay
from RESETâ to Qnâ
from RESETâ to PPOâ
-
-
-
-
tPLH
LOW-to-HIGH propagation delay
from RESETâ to QERRâ
-
-
[1] Includes 350 ps of test load transmission line delay.
[2] This parameter is not necessarily production tested.
Max Unit
-
MHz
1.4 ns
1.7 ns
3
ns
2.4 ns
1.5 ns
3
ns
3
ns
3
ns
Table 11. Data output edge rates
At recommended operating conditions (see Table 7), unless otherwise speciï¬ed. See Section 11.2.
Symbol Parameter
Conditions
Min Typ
dV/dt_r
rising edge slew rate
from 20 % to 80 %
1
-
dV/dt_f
falling edge slew rate
from 80 % to 20 %
1
-
dV/dt_â
absolute difference between dV/dt_r from 20 % or 80 %
and dV/dt_f
to 80 % or 20 %
-
-
Max Unit
4
V/ns
4
V/ns
1
V/ns
SSTUG32866_1
Product data sheet
Rev. 01 â 29 June 2007
© NXP B.V. 2007. All rights reserved.
13 of 28
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