SC18IS602 Datasheet, PDF (13/25 Pages) NXP Semiconductors – I2C-bus to SPI bridge

NXP Semiconductors
SC18IS602/602B/603
I²C-bus to SPI bridge
7.2 External clock input (SC18IS603)
In this device, the processor clock is derived from an external source driving the CLKIN
pin. The rate may be from 0 Hz up to 18 MHz.
Using the external clock allows higher frequencies from the SPI interface, thus the
SPI Master operating can be up to 4 Mbit/s. The CLKIN frequency does not affect the
clock speed of the I²C-bus interface, however, it will have an effect on the low period
between bytes on the I²C-bus.
7.3 SPI interface
The SPI interface can support Mode 0 through Mode 3 of the SPI specification and can
operate up to 1.8 Mbit/s (SC18IS602/602B) or 4.0 Mbit/s (SC18IS603). The SPI interface
uses at least four pins: SPICLK, MOSI, MISO, and Slave Select (SSn).
SSn are the slave select pins. In a typical configuration, an SPI master selects one SPI
device as the current slave.
There are actually four SSn pins (SS0, SS1, SS2 and SS3) to allow the
SC18IS602/602B/603 to communicate with multiple SPI devices.
The SC18IS602/602B/603 generates the SPICLK (SPI clock) signal in order to send and
receive data. The SCLK, MOSI, and MISO are typically tied together between two or more
SPI devices. Data flows from the SC18IS602/602B/603 (master) to slave on the MOSI pin
(Pin 6) and the data flows from slave to SC18IS602/602B/603 (master) on the MISO pin
(Pin 5).
SC18IS602_602B_603_4
Product data sheet
Rev. 04 — 11 March 2008
© NXP B.V. 2008. All rights reserved.
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