PCA9541_09 Datasheet, PDF (13/41 Pages) NXP Semiconductors – 2-to-1 I2C-bus master selector with interrupt logic and reset

NXP Semiconductors
PCA9541
2-to-1 I²C-bus master selector with interrupt logic and reset
Table 11. Default Control Register values
Type version Master Bit 7
Bit 6
NTESTON TESTON
PCA9541/01 MST_0
0
0
MST_1
0
0
PCA9541/03 MST_0
0
0
MST_1
0
0
Bit 5
not used
0
0
0
0
Bit 4
BUSINIT
0
0
0
0
Bit 3
NBUSON
0
1
0
0
Bit 2
BUSON
1
0
0
0
Bit 1
NMYBUS
0
1
0
1
Bit 0
MYBUS
0
0
0
0
Table 12 describes which command needs to be written to the Control Register when a
master device wants to take control of the I²C-bus. Byte written to the Control Register is a
function of the current I²C-bus control status performed after an initial reading of the
Control Register.
Current status of the I²C-bus is determined by the bits MYBUS, NMYBUS, BUSON and
NBUSON is one of the following:
• The master reading its Control Register does not have control and the I²C-bus is off.
• The master reading its Control Register does not have control and the I²C-bus is on.
• The master reading its Control Register has control and the I²C-bus is off.
• The master reading its Control Register has control and the I²C-bus is on.
‘I²C-bus off’ means that upstream and downstream channels are not connected together.
‘I²C-bus on’ means that upstream and downstream channels are connected together.
Remark: Only the 4 LSBs of the Control Register are described in Table 12 since only
those bits control the I²C-bus control. The logic value for the 4 MSBs is specific to the
application and are not discussed in the table.
The read sequence is performed by the master as:
S - 111xxxx0 - 000x0001 - Sr - 111xxxx1 - DataRead - P
The write sequence is performed by the master as:
S - 111xxxx0 - 000x0001 - DataWritten - P
PCA9541_7
Product data sheet
Rev. 07 — 2 July 2009
© NXP B.V. 2009. All rights reserved.
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