74AUP1G38 Datasheet, PDF (13/15 Pages) NXP Semiconductors – Low-power 2-input NAND gate (open drain)

NXP Semiconductors
74AUP1G38
Low-power 2-input NAND gate (open drain)
14. Abbreviations
Table 11. Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date Data sheet status
Change notice
Supersedes
74AUP1G38_3
Modifications:
20090622
Product data sheet
-
74AUP1G38_2
• Table 5: Derating factor XSON8 and XQFN8U has been changed.
74AUP1G38_2
20070614
Product data sheet
-
74AUP1G38_1
74AUP1G38_1
20061020
Product data sheet
-
-
74AUP1G38_3
Product data sheet
Rev. 03 — 22 June 2009
© NXP B.V. 2009. All rights reserved.
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