UJA1163 Datasheet, PDF (12/28 Pages) NXP Semiconductors – Mini high-speed CAN system basis chip with Standby mode

NXP Semiconductors
UJA1163
Mini high-speed CAN system basis chip with Standby mode
6.7 CAN fail-safe features
6.7.1 TXD dominant timeout
A TXD dominant time-out timer is started when pin TXD is forced LOW while the
transceiver is in CAN Active Mode. If the LOW state on pin TXD persists for longer than
the TXD dominant time-out time (t_to(dom)TXD), the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD goes HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 15 kbit/s.
6.7.2 Pull-up on TXD pin
Pin TXD has an internal pull-up towards V1 to ensure a safe defined recessive driver state
in case the pin is left floating.
6.7.3 Pull-down on STBN pin
Pin STBN has an internal pull-down (to GND) to ensure the UJA1163 switches to Standby
mode if STBN is left floating.
6.7.4 Loss of power at pin BAT
A loss of power at pin BAT has no influence on the bus lines or on the microcontroller. No
reverse currents will flow from the bus.
UJA1163
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 1 October 2013
© NXP B.V. 2013. All rights reserved.
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