SAF1562 Datasheet, PDF (12/97 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

NXP Semiconductors
SAF1562
Hi-Speed Universal Serial Bus PCI Host Controller
Each function has its own configuration space. The PCI enumerator should allocate the
memory address space for each of these functions. Power management is implemented
in each PCI function and all power states are provided. This allows the system to achieve
low power consumption by switching off the functions that are not required.
8.1.1 PCI configuration space
PCI Local Bus Specification Rev. 2.2 requires that each of the three PCI functions of the
SAF1562HL provides its own PCI configuration registers, which can vary in size. In
addition to the basic PCI configuration header registers, these functions implement
capability registers to support power management.
The registers of each of these functions are accessed by the respective driver. Section 8.2
provides a detailed description of the various PCI configuration registers.
8.1.2 PCI initiator and target
A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI
transactions as a slave. In the case of the SAF1562HL, the two Open Host Controllers
and the Enhanced Host Controller function as both initiators or targets of PCI transactions
issued by the host CPU.
All USB Host Controllers have their own operational registers that can be accessed by the
system driver software. Drivers use these registers to configure the Host Controller
hardware system, issue commands to it, and monitor the status of the current hardware
operation. The Host Controller plays the role of a PCI target. All operational registers of
the Host Controllers are the PCI transaction targets of the CPU.
Normal USB transfers require the Host Controller to access system memory fields, which
are allocated by USB HCDs and PCI drivers. The Host Controller hardware interacts with
the HCD by accessing these buffers. The Host Controller works as an initiator in this case
and becomes a PCI master.
8.2 PCI configuration registers
The OHCI USB Host Controllers and the EHCI USB Host Controller contain two sets of
software-accessible hardware registers: PCI configuration registers and memory-mapped
Host Controller registers.
A set of configuration registers is implemented for each of the three PCI functions of the
SAF1562HL, see Table 3.
Remark: In addition to the normal PCI header, from offset index 00h to 3Fh,
implementation-specific registers are defined to support power management and
function-specific features.
Table 3. PCI configuration space registers of OHCI1, OHCI2 and EHCI
Address Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Bits 7 to 0
Reset value^[1]
Func0 OHCI1 Func1 OHCI2 Func2 EHCI
PCI configuration header registers
00h
Device ID[15:0]
Vendor ID[15:0]
1561 1131h 1561 1131h 1562 1131h
04h
Status[15:0]
Command[15:0]
0210 0000h 0210 0000h 0210 0000h
SAF1562_1
Product data sheet
Rev. 01 — 7 February 2007
© NXP B.V. 2007. All rights reserved.
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