PN7150B0HN Datasheet, PDF (11/55 Pages) NXP Semiconductors – High performance full NFC Forum-compliant controller with integrated firmware and NCI interface

NXP Semiconductors
PN7150
Full NFC Forum-compliant controller with integrated firmware
Table 8. PN7150 power states
Power state name Description
Monitor
The PN7150 is supplied by V_BAT which voltage is below its programmable
critical level, VEN voltage > 1.1 V and the Monitor state is enabled. The
system power mode is Power Off mode.
Hard Power Down
The PN7150 is supplied by V_BAT which voltage is above its programmable
critical level when Monitor state is enabled and PN7150 is kept in Hard
Power Down (VEN voltage is kept low by host or SW programming) to have
the minimum power consumption. The system power mode is in Power Off.
Standby
The PN7150 is supplied by V_BAT which voltage is above its programmable
critical level when the Monitor state is enabled, VEN voltage is high (by host
or SW programming) and minimum part of PN7150 is kept supplied to enable
configured wake-up sources which allow to switch to Active state; RF field,
Host interface. The system power mode is Full power mode.
Active
The PN7150 is supplied by V_BAT which voltage is above its programmable
critical level when Monitor state is enabled, VEN voltage is high (by host or
SW programming) and the PN7150 internal blocks are supplied. 3 functional
modes are defined: Idle, Target and Initiator. The system power mode is Full
power mode.
At application level, the PN7150 will continuously switch between different states to
optimize the current consumption (polling loop mode). Refer to Table 1 for targeted
current consumption in here described states.
The PN7150 is designed to allow the host controller to have full control over its functional
states, thus of the power consumption of the PN7150 based NFC solution and possibility
to restrict parts of the PN7150 functionality.
10.1.2.1 Monitor state
In Monitor state, the PN7150 will exit it only if the battery voltage recovers over the critical
level. Battery voltage monitor thresholds show hysteresis behavior as defined in Table 27.
10.1.2.2 Hard Power Down (HPD) state
The Hard Power Down state is entered when V_DD(PAD) and V_BAT are high by setting VEN
voltage < 0.4 V. As these signals are under host control, the PN7150 has no influence on
entering or exiting this state.
10.1.2.3 Standby state
Active state is PN7150’s default state after boot sequence in order to allow a quick
configuration of PN7150. It is recommended to change the default state to Standby state
after first boot in order to save power. PN7150 can switch to Standby state autonomously
(if configured by host).
In this state, PN7150 most blocks including CPU are no more supplied. Number of
wake-up sources exist to put PN7150 into Active state:
• I²C-bus interface wake-up event
• Antenna RF level detector
• Internal timer event when using polling loop (380 kHz Low-power oscillator is
enabled)
PN7150
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 4 July 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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