P82B96TD-T Datasheet, PDF (11/32 Pages) NXP Semiconductors – Dual bidirectional bus buffer

NXP Semiconductors
P82B96
Dual bidirectional bus buffer
Figure 13 shows how a master I²C-bus can be protected against short circuits or failures
in applications that involve plug and socket connections and long cables that may become
damaged. A simple circuit is added to monitor the SDA bus, and if its LOW time exceeds
the design value, then the master bus is disconnected. P82B96 will free all its I/Os if its
supply is removed, so one option is to connect its V_CC to the output of a logic gate from,
say, the 74LVC family. The SDA and SCL lines could be timed and V_CC disabled via the
gate if one or other lines exceeds a design value of ‘LOW’ period as in Figure 28 of
AN255. If the supply voltage of logic gates restricts the choice of V_CC supply then the
low-cost discrete circuit in Figure 13 can be used. If the SDA line is held LOW, the 100 nF
capacitor will charge and the Ry input will be pulled towards V_CC. When it exceeds 0.5V_CC
the Ry input will set the Sy input HIGH, which in practice means simply releasing it.
In this example the SCL line is made unidirectional by tying the Rx pin to V_CC. The state of
the buffered SCL line cannot affect the master clock line which is allowed when
clock-stretching is not required. It is simple to add an additional transistor or diode to
control the Rx input in the same way as Ry when necessary. The +V cable drive can be
any voltage up to 15 V and the bus may be run at a lower impedance by selecting pull-up
resistors for a static sink current up to 30 mA. V_CC1 and V_CC2 may be chosen to suit the
connected devices. Because DDC uses relatively low speeds (< 100 kHz), the cable
length is not restricted to 20 m by the I²C-bus signalling, but it may be limited by the video
signalling.
V_CC1
SCL
I²C-bus/DDC
master
SDA
GND
V_CC
+V cable drive
100 nF
100
kΩ
+V cable drive
V_CC
Rx BC
847B
Sx
Tx
3 m to 20 m
Rx
cables
Tx
Sx
Ry
4.7 kΩ
Sy
Ty
P82B96 ^{470 kΩ}
470 kΩ
BC
847B
PC/TV receiver/decoder box
Ry
I²C-bus/DDC
Ty
Sy
P82B96
R
G
B
video signals
monitor/flat TV
Fig 13. Extending a DDC bus
V_CC2
SCL
I²C-bus/DDC
slave
SDA
GND
002aab989
P82B96_8
Product data sheet
Rev. 08 — 10 November 2009
© NXP B.V. 2009. All rights reserved.
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