74ALVC162334A Datasheet, PDF (11/19 Pages) NXP Semiconductors – 16-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

NXP Semiconductors
74ALVC162334A
16-bit registered driver (3-state)
11.1 AC waveforms
V_CC = 3.0 V to 3.6 V and V_CC = 2.7 V range:
V_M = 1.5 V; V_X = V_OL + 0.3 V; V_Y = V_OH − 0.3 V; V_I = 2.7 V.
V_OL and V_OH are the typical output voltage drop that occur with the output load.
V_CC = 2.3 V to 2.7 V and V_CC < 2.3 V range:
V_M = 0.5 V; V_X = V_OL + 0.15 V; V_Y = V_OH − 0.15 V; V_I = V_CC.
V_OL and V_OH are the typical output voltage drop that occur with the output load.
An input
Yn output
V_M
t_PHL
V_M
t_PLH
V_I
GND
V_OH
V_OL
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Fig 5. Input (An) to output (Yn) propagation delay
An
input
LE
input
V_M
t_su
t_h
V_M
V_M
t_su
V_I
GND
t_h
V_I
V_M
GND
002aac728
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
Fig 7. Data set-up and hold times, An input to
LE input
CP
input
An
input
V_M
t_su t_h
t_su t_h
V_I
GND
V_I
GND
Yn
output
V_OH
V_OL
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The shaded areas indicate when the input is
permitted to change for predictable output
performance.
Fig 9. Data set-up and hold times, An input to
CP input
LE input
Yn output
V_M
t_w
t_PHL
V_M
V_M
t_PLH
V_I
GND
V_OH
V_OL
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Fig 6. LE input pulse width, LE input to Yn output
propagation delays
CP input
Yn output
1 / f_max
V_M
t_w
t_PHL
V_M
V_M
t_PLH
V_I
GND
V_OH
V_OL
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Fig 8. CP to Yn propagation delays, clock pulse width,
and maximum clock frequency
OE input
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
V_M
t_PLZ
t_PHZ
outputs
enabled
V_I
t_PZL
V_X
V_Y
t_PZH
outputs
disabled
GND
V_CC
V_M
V_OL
V_OH
V_M
GND
outputs
enabled
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Fig 10. 3-state enable and disable times
74ALVC162334A_3
Product data sheet
Rev. 03 — 13 December 2006
© NXP B.V. 2006. All rights reserved.
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