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HEF4516B_09 Datasheet, PDF (10/16 Pages) NXP Semiconductors – Binary up/down counter
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NXP Semiconductors
HEF4516B
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Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; CL = 50 pF; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter
VDD
Typical formula for PD (μW)
Where:
PD
dynamic power 5 V
PD = 1000 × fi + Σ(fo × CL) × VDD2
fi = input frequency in MHz;
dissipation
10 V
PD = 4500 × fi + Σ(fo × CL) × VDD2
fo = output frequency in MHz;
15 V
PD = 11200 × fi + Σ(fo × CL) × VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
Σ(fo × CL) = sum of the outputs.
12. Waveforms
tW
VI
CP input
VM
VSS
tsu
th
VI
CE input
VM
VSS
tsu
th
tsu
th
VI
UP/DN input
VM
VSS
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Measurement points are given in Table 9.
Fig 6. Waveforms showing minimum pulse width for CP, set-up and hold times for CE to CP and UP/DN to CP
VI
CP input
VSS
VI
PL input
VSS
VI
Dn input
VSS
VI
MR input
VSS
tW
VM
tsu
VM
VM
trec
th
trec
VM
tW
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Fig 7.
Measurement points are given in Table 9.
Waveforms showing PL and MR minimum pulse widths and recovery times, and Dn to PL set-up and hold
times
HEF4516B_6
Product data sheet
Rev. 06 — 11 December 2009
© NXP B.V. 2009. All rights reserved.
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