ADC1413D065 Datasheet, PDF (10/38 Pages) NXP Semiconductors – Dual 14 bits ADC; 65, 80, 105 or 125 Msps; serial JESD204A interface

NXP Semiconductors
ADC1413D065/080/105/125
Dual 14 bits ADC; 65, 80, 105 or 125 Msps
Table 6. Characteristics …continued
Typical values measured at V_DDA = 3 V, V_DDD = 1.8 V, T_amb = 25 °C and C_L = 5 pF.
Min. and max. values are across the full temperature range T_amb = −40 °C to +85 °C at V_DDA = 3 V, V_DDD = 1.8 V;
V_i (INAP, INBP) − V_i (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol Parameter
Conditions
ADC1413D065 ADC1413D080 ADC1413D105 ADC1413D12 Unit
5
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
SNR
SFDR
IMD
α_ct(ch)
signal-to-noise
ratio
spurious-free
dynamic range
intermodulation
distortion
crosstalk
between
channels
f_i = 3 MHz
f_i = 30 MHz
f_i = 70 MHz
f_i = 170 MHz
f_i = 3 MHz
f_i = 30 MHz
f_i = 70 MHz
f_i = 170 MHz
f_i = 3 MHz
f_i = 30 MHz
f_i = 70 MHz
f_i = 170 MHz
f_i = 70 MHz
- 73.2 - - 73.1 - -
- 72.4 - - 72.3 - -
- 71.8 - - 71.8 - -
- 71.3 - - 71.2 - -
- 91 - - 91 - -
- 90 - - 90 - -
- 89 - - 89 - -
- 86 - - 86 - -
- 94 - - 94 - -
- 93 - - 93 - -
- 92 - - 92 - -
- 89 - - 89 - -
- ^tbd - - ^tbd - -
72.9 -
72.3 -
71.7 -
71.1 -
90 -
90 -
88 -
85 -
93 -
93 -
91 -
88 -
tbd _-
- 72.5 - dBFS
- 72.2 - dBFS
- 71.6 - dBFS
- 71 - dBFS
- 90 - dBc
- 89 - dBc
- 87 - dBc
- 85 - dBc
- 93 - dBc
- 92 - dBc
- 90 - dBc
- 88 - dBc
- ^tbd - dB
11. Clock and digital output timing
Table 7. Characteristics
Typical values measured at V_DDA = 3 V, V_DDD = 1.8 V, T_amb = 25 °C and C_L = 5 pF.
Min. and max. values are across the full temperature range T_amb = −40 °C to +85 °C at V_DDA = 3 V, V_DDD = 1.8 V;
V_I (INAP, INBP) − V_I (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless
otherwise specified.
Symbol Parameter
Conditions ADC1413D065 ADC1413D080 ADC1413D105 ADC1413D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock timing input: pins CLKP and CLKM
f_clk
t_lat(data)
clock frequency
data latency
time
20 -
17 -
65 60 -
20 17 -
80 60 -
20 17 -
105 60 -
20 17 -
125 Msps
20 clk/cy
δ_clk
clock duty cycle DCS en
30 50 70 30 50 70 30 50 70 30 50 70 %
DCS dis
45 50 55 45 50 55 45 50 55 45 50 55 %
t_d(s)
t_wake
sampling delay
time
wake-up time
- 0.8 - - 0.8 - - 0.8 - - 0.8 - ns
- ^tbd - - ^tbd - - ^tbd - - ^tbd - ns
11.1 Serial output timings
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
ADC1413D065_080_105_125_2
Objective data sheet
Rev. 02 — 4 June 2009
© NXP B.V. 2009. All rights reserved.
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