74HC123D.653 Datasheet, PDF(10/25 Page) NXP Semiconductors – Dual retriggerable monostable multivibrator with reset

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

74HC123D.653 Datasheet, PDF (10/25 Pages) NXP Semiconductors – Dual retriggerable monostable multivibrator with reset

◁

NXP Semiconductors

74HC123; 74HCT123

Dual retriggerable monostable multivibrator with reset

Table 7. Dynamic characteristics â¦continued

Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.

Symbol Parameter Conditions

25 ï°C

ï40 ï°C to +85 ï°C ï40 ï°C to +125 ï°C Unit

Min Typ Max Min Max Min Max

pulse width VCC = 4.5 V

nA LOW; see Figure 10

20 3 -

- ns

nB HIGH; see Figure 10

20 5 -

- ns

nRD LOW; see Figure 11

20 7 -

- ns

nQ HIGH and nQ LOW;

[2]

VCC = 5.0 V;

see Figure 10 and 11

CEXT = 100 nF;

REXT = 10 kï

- 450 -

- ïs

CEXT = 0 pF;

REXT = 5 kï

- 75 -

- ns

trtrig

retrigger time nA, nB; CEXT = 0 pF;

[3][4] - 110 -

- ns

REXT = 5 kï; VCC = 5.0 V;

see Figure 10

REXT external timing VCC = 5.0 V; see Figure 7

- 1000 -

- kï

resistor

CEXT external timing VCC = 5.0 V; see Figure 7 [4] -

- pF

capacitor

CPD

power

per monostable;

dissipation

VI = GND to VCC

capacitance

[5] -

- pF

[1] tpd is the same as tPHL and tPLH; tt is the same as tTHL and tTLH

[2] For other REXT and CEXT combinations see Figure 7. If CEXT > 10 nF, the next formula is valid.

tW = K ï´ REXT ï´ CEXT, where:

tW = typical output pulse width in ns;

REXT = external resistor in kï;

CEXT = external capacitor in pF;

K = constant = 0.45 for VCC = 5.0 V and 0.55 for VCC = 2.0 V.

The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is approximately 7 pF.

[3] The time to retrigger the monostable multivibrator depends on the values of REXT and CEXT. The output pulse width will only be

extended when the time between the active-going edges of the trigger input pulses meets the minimum retrigger time. If CEXT >10 pF,

the next formula (at VCC = 5.0 V) for the setup time of a retrigger pulse is valid:

trtrig = 30 + 0.19 ï´ REXT ï´ CEXT0.9 + 13 ï´ REXT1.05, where:

trtrig = retrigger time in ns;

CEXT = external capacitor in pF; REXT = external resistor in kï.

The inherent test jig and pin capacitance at pins 15 and 7 (nREXT/CEXT) is 7 pF.

[4] When the device is powered-up, initiate the device via a reset pulse, when CEXT < 50 pF.

[5] CPD is used to determine the dynamic power dissipation (PD in ïW).

PD = CPD ï´ VCC2 ï´ fi + ï¥(CL ï´ VCC2 ï´ fo) + 0.75 ï´ CEXT ï´ VCC2 ï´ fo + D ï´ 16 ï´ VCC where:

fi = input frequency in MHz;

fo = output frequency in MHz;

D = duty factor in %;

CL = output load capacitance in pF;

VCC = supply voltage in V;

CEXT = timing capacitance in pF;

ï¥(CL ï´ VCC2 ï´ fo) sum of outputs.

74HC_HCT123

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 8 â 16 December 2011

10 of 25

▷