SSTUA32S865 Datasheet, PDF (1/29 Pages) NXP Semiconductors – 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications

SSTUA32S865
1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667
RDIMM applications
Rev. 02 — 16 March 2007
Product data sheet
1. General description
The SSTUA32S865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two
rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory
modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but
integrates the functionality of the normally required two registers in a single package,
thereby freeing up board real-estate and facilitating routing to accommodate high-density
Dual In-line Memory Module (DIMM) designs.
The SSTUA32S865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
The SSTUA32S865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum
9 mm × 13 mm of board space) allows for adequate signal routing and escape using
conventional card technology.
2. Features
I 28-bit data register supporting DDR2
I Fully compliant to JEDEC standard for SSTUA32S865
I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2 × SSTUA32864 or 2 × SSTUA32866)
I Parity checking function across 22 input data bits
I Parity out signal
I Controlled output impedance drivers enable optimal signal integrity and speed
I Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation
delay, 2.0 ns max. mass-switching)
I Supports up to 450 MHz clock frequency of operation
I Optimized pinout for high-density DDR2 module design
I Chip-selects minimize power consumption by gating data outputs from changing state
I Supports Stub Series Terminated Logic SSTL_18 data inputs
I Differential clock (CK and CK) inputs
I Supports Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
switching levels on the control and RESET inputs
I Single 1.8 V supply operation (1.7 V to 2.0 V)
I Available in 160-ball 9 mm × 13 mm, 0.65 mm ball pitch TFBGA package