PHKD6N02LT Datasheet, PDF (1/13 Pages) NXP Semiconductors – Dual TrenchMOS logic level FET

PHKD6N02LT
Dual N-channel TrenchMOS logic level FET
Rev. 04 — 27 April 2010
Product data sheet
1. Product profile
1.1 General description
Dual logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Suitable for logic level gate drive
sources
1.3 Applications
„ Battery chargers
„ DC-to-DC convertors
„ Notebook computers
„ Portable equipment
1.4 Quick reference data
Table 1. Quick reference data
Symbol Parameter
Conditions
V_DS
drain-source voltage T_j ≥ 25 °C; T_j ≤ 150 °C
I_D
drain current
T_sp = 25 °C; Single device
conducting; see Figure 1;
see Figure 3
P_tot
total power
dissipation
T_sp = 25 °C; see Figure 2
Static characteristics
R_DSon
drain-source on-state V_GS = 2.5 V; I_D = 3 A; T_j = 25 °C
resistance
Dynamic characteristics
Q_GD
gate-drain charge
V_GS = 5 V; I_D = 6 A; V_DS = 16 V;
T_j = 25 °C; see Figure 11
Min Typ Max Unit
-
-
20 V
-
-
10.9 A
-
-
4.17 W
-
25 35 mΩ
-
6-
nC