PHK04P02T_10 Datasheet, PDF (1/12 Pages) NXP Semiconductors – P-channel vertical D-MOS logic level FET Battery powered applications

PHK04P02T
P-channel vertical D-MOS logic level FET
Rev. 02 — 14 December 2010
Product data sheet
1. Product profile
1.1 General description
Logic level P-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using vertical D-MOS technology. This product is designed and qualified for use
in computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Suitable for high frequency
applications due to fast switching
characteristics
„ Suitable for logic level gate drive
sources
„ Suitable for very low gate drive
sources voltage
1.3 Applications
„ Battery powered applications
„ High-speed digital interfaces
1.4 Quick reference data
Table 1.
Symbol
V_DS
I_D
Quick reference data
Parameter
Conditions
drain-source voltage T_j ≥ 25 °C; T_j ≤ 150 °C
drain current
T_sp = 25 °C
P_tot
total power
dissipation
Static characteristics
R_DSon
drain-source on-state
resistance
Dynamic characteristics
V_GS = -2.5 V; I_D = -1 A; T_j = 25 °C
V_GS = -4.5 V; I_D = -1 A; T_j = 25 °C
Q_GD
gate-drain charge
V_GS = -4.5 V; I_D = -1 A;
V_DS = -10 V; T_j = 25 °C
Min Typ Max Unit
-
-
-16 V
-
-
-4.6 A
6
-
-
5
W
-
117 150 mΩ
-
80 120 mΩ
-
1.83 -
nC