PHD96NQ03LT Datasheet, PDF (1/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

PHD96NQ03LT
N-channel TrenchMOS logic level FET
Rev. 06 — 15 March 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Simple gate drive required due to low
gate charge
1.3 Applications
„ DC-to-DC convertors
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
V_DS
drain-source voltage T_j ≥ 25 °C; T_j ≤ 175 °C
I_D
drain current
T_mb = 25 °C; V_GS = 5 V;
see Figure 1 and 3
P_tot
total power
dissipation
T_mb = 25 °C; see Figure 2
Dynamic characteristics
Q_GD
gate-drain charge V_GS = 5 V; I_D = 50 A;
V_DS = 15 V; T_j = 25 °C;
see Figure 11
Static characteristics
R_DSon
drain-source
on-state resistance
V_GS = 10 V; I_D = 25 A;
T_j = 25 °C; see Figure 9
V_GS = 5 V; I_D = 25 A;
T_j = 25 °C;
see Figure 9 and 10
Min Typ Max Unit
-
-
25 V
-
-
75 A
-
-
115 W
-
8.4 -
nC
-
4.2 4.95 mΩ
-
5.6 7.5 mΩ