|
PHD71NQ03LT Datasheet, PDF (1/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET | |||
|
PHD71NQ03LT
N-channel TrenchMOS logic level FET
Rev. 02 â 9 March 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
 Simple gate drive required due to low
gate charge
 Suitable for logic level gate drive
sources
1.3 Applications
 DC-to-DC convertors
 Switched-mode power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
VDS
drain-source voltage Tj ⥠25 °C; Tj ⤠175 °C
ID
drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1 and 3
Ptot
total power dissipation Tmb = 25 °C; see Figure 2
Dynamic characteristics
QGD
gate-drain charge
VGS = 5 V; ID = 50 A;
VDS = 15 V; Tj = 25 °C;
see Figure 11
Static characteristics
RDSon
drain-source on-state VGS = 10 V; ID = 25 A;
resistance
Tj = 25 °C; see Figure 9
Min Typ Max Unit
-
-
30 V
-
-
75 A
-
-
120 W
-
4.6 -
nC
-
8
10 mâ¦
|
▷ |