PHD38N02LT Datasheet, PDF (1/12 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

PHD38N02LT
N-channel TrenchMOS logic level FET
Rev. 02 — 2 February 2007
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
I Low on-state resistance
I 2.5 V gate drive
1.3 Applications
I Linear regulator for Double-Data Rate (DDR) memory
1.4 Quick reference data
I V_DS ≤ 20 V
I R_DSon ≤ 16 mΩ
I I_D ≤ 44.7 A
I P_tot ≤ 57.6 W
2. Pinning information
Table 1. Pinning
Pin
Description
1
gate (G)
2
drain (D)
3
source (S)
mb
mounting base; connected to drain (D)
Simplified outline
[1]
mb
[1] It is not possible to make a connection to pin 2.
2
1
3
SOT428 (DPAK)
Symbol
D
G
mbb076 S