PH955L Datasheet, PDF (1/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

PH955L
N-channel TrenchMOS logic level FET
Rev. 02 — 19 February 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Suitable for logic level gate drive
sources
1.3 Applications
„ DC-to-DC convertors
„ General purpose power switching
„ Motors, lamps and solenoids
„ Portable equipment
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
V_DS
drain-source voltage T_j ≥ 25 °C; T_j ≤ 150 °C
I_D
drain current
T_mb = 25 °C; V_GS = 5 V;
see Figure 1; see Figure 3
P_tot
total power
dissipation
T_mb = 25 °C; see Figure 2
Dynamic characteristics
Q_GD
gate-drain charge V_GS = 5 V; I_D = 25 A;
V_DS = 44 V; T_j = 25 °C;
see Figure 11; see Figure 12
Static characteristics
R_DSon
drain-source
V_GS = 10 V; I_D = 25 A;
on-state resistance T_j = 25 °C; see Figure 10
Min Typ Max Unit
-
-
55 V
-
-
62.5 A
-
-
62.5 W
-
16.4 -
nC
-
6.2 8.3 mΩ