PH1825AL Datasheet, PDF (1/13 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

PH1825AL
N-channel TrenchMOS logic level FET
Rev. 01 — 22 April 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ 100% gate resistance tested
„ 100% Ruggedness tested
„ Lead-free package
„ Logic level compatible
„ Optimimzed for use in DC-to-DC
converters
„ Very low switching and conduction
losses
1.3 Applications
„ DC-to-DC converters
„ Notebook computers
„ Switched-mode power supplies
„ Voltage regulators
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
V_DS
drain-source voltage T_j ≥ 25 °C; T_j ≤ 150 °C
-
-
25 V
I_D
drain current
T_mb = 25 °C; V_GS = 10 V; [1] -
-
100 A
see Figure 1; see Figure 3
Dynamic characteristics
Q_GD
gate-drain charge V_GS = 4.5 V; I_D = 25 A;
V_DS = 12 V; see Figure 12;
see Figure 13
-
8
-
nC
Static characteristics
R_DSon
drain-source
on-state resistance
V_GS = 10 V; I_D = 25 A;
T_j = 25 °C; see Figure 10;
see Figure 11
-
1.4 1.8 mΩ
[1] Continuous current is limited by package.