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PCKEL14 Datasheet, PDF (1/15 Pages) NXP Semiconductors – 2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip | |||
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PCKEL14
2.5 V/3.3 V PECL/ECL 1:5 clock distribution chip
Rev. 01 â 14 October 2002
Product data
1. Description
The PCKEL14 is a low skew 1:5 clock distribution chip designed explicitly for low
skew clock distribution applications. The device can be driven by either a differential
or single-ended ECL, or if positive power supplies are used, PECL input signal. The
PCKEL14 is designed to operate in ECL or PECL mode for a voltage supply range of
â2.375 V to â3.8 V (or 2.375 V to 3.8 V).
The PCKEL14 features a multiplexed clock input to allow for the distribution of a lower
speed scan or test clock along with the high speed system clock. When LOW (or left
open and pulled LOW by the input pull-down resistor), the SEL pin will select the
differential clock input.
The common enable (EN) is synchronous, so that the outputs will only be
enabled/disabled when they are already in the LOW state. This avoids any chance of
generating a runt clock pulse when the device is enabled/disabled, as can happen
with an asynchronous control. The internal ï¬ip-ï¬op is clocked on the falling edge of
the input clock, therefore all associated speciï¬cation limits are referenced to the
negative edge of the clock input.
The VBB pin (an internally generated voltage supply) is available to this device only.
For single-ended conditions, the unused differential input is connected to VBB as a
switching reference voltage. VBB may also rebias AC-coupled inputs. When used,
decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to
0.1 mA. When not used, VBB should be left open.
2. Features
s 50 ps output-to-output skew at 3.3 V
s Synchronous enable/disable
s Multiplexed clock input
s ESD protection: > 2.5 kV HBM
s The PCK series contains temperature compensation
s PECL mode operating range: VCC = 2.375 V to 3.8 V, with VEE = 0 V
s NECL mode operating range: VCC = 0 V, with VEE = â2.375 V to â3.8 V
s Internal 75 k⦠pull-down resistors on all inputs, plus a 37.5 k⦠pull-up on CLK
s Q output will default LOW with inputs open or at VEE
s Meets or exceeds JEDEC spec EIA/JESD78 IC latch-up test
s Moisture sensitivity level 1
s Flammability rating: UL-94 code V-0 @ 1/8â
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