PCA9558 Datasheet, PDF (1/27 Pages) NXP Semiconductors – 8-bit I2C and SMBus I/O port with 5-bit multiplexed/1-bit latched 6-bit I2C EEPROM and 2 k bit EEPROM

PCA9558
8-bit I²C-bus and SMBus I/O port with 5-bit multiplexed/1-bit
latched 6-bit I²C-bus EEPROM DIP switch and 2-kbit EEPROM
Rev. 04 — 14 April 2009
Product data sheet
1. General description
The PCA9558 is a highly integrated, multi-function device that is composed of a 5-bit
multiplexed/1-bit latched 6-bit I²C-bus/SMBus EEPROM DIP switch, an 8-bit I/O expander
and a 2-kbit serial EEPROM with write protect. The PCA9558 integrates these commonly
used components into a single chip to reduce component count and board space
requirements and is useful in computer, server and telecom/networking applications.
• Multiplexed/latched EEPROM DIP switch—used to select digital information
between a set of 5 bits of default hardware inputs and an alternative set of inputs
provided by the I²C-bus/SMBus interface and stored in the EEPROM. Examples of
this type of selection include processor voltage configuration or processor vendor
identification (VID). The multiplexed/latched EEPROM can also be used to replace
DIP switches or jumpers, since the settings can be easily changed via I²C-bus/SMBus
without having to power down the equipment to open the cabinet. The non-volatile
memory retains the most current setting selected before the power is turned off.
• 8-bit I/O expander—used to control, monitor or collect remote information or power
LEDs. Monitored or collected information can be read through the I²C-bus/SMBus or
can be stored in the internal EEPROM.
• 2-kbit serial EEPROM—used to store information such as card identification or
revision/maintenance history on every motherboard/line card and can be read or
written via I²C-bus/SMBus when required.
The PCA9558 has 1 address pin, allowing up to 2 devices to be placed on the same
I²C-bus or SMBus.
2. Features
I 5-bit 2-to-1 multiplexer, 1-bit latch DIP switch
I 6-bit MUX_OUTx and NON_MUXED_OUT EEPROM programmable and readable via
I²C-bus
I 5 V tolerant open-drain MUX_OUTx and NON_MUXED_OUT outputs
I Active LOW override input forces all MUX_OUTx outputs to logic 0
I I²C-bus readable MUX_INx inputs
I 5 V tolerant open-drain IOx pins, power-up default as outputs
I 1 address pin, allowing up to 2 devices on the I²C-bus
I Active LOW reset input with internal pull-up for the 8 I/O pins
I 2048-bit EEPROM programmable and readable via the I²C-bus or I/Os
I Operating power supply voltage range of 3.0 V to 3.6 V
I SMBus compliance with fixed 3.3 V levels