PCA9557 Datasheet, PDF (1/26 Pages) NXP Semiconductors – 8-bit I2C and SMBus I/0 port with reset

PCA9557
8-bit I²C-bus and SMBus I/O port with reset
Rev. 06 — 11 June 2008
Product data sheet
1. General description
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for
SMBus and I²C-bus applications. The PCA9557 consists of an 8-bit input port register,
8-bit output port register, and an I²C-bus/SMBus interface. It has low current consumption
and a high-impedance open-drain output pin, IO0.
The system master can enable the PCA9557’s I/O as either input or output by writing to
the configuration register. The system master can also invert the PCA9557 inputs by
writing to the active HIGH polarity inversion register. Finally, the system master can reset
the PCA9557 in the event of a time-out by asserting a LOW in the reset input.
The power-on reset puts the registers in their default state and initializes the
I²C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to
occur without de-powering the part.
2. Features
I Lower voltage, higher performance migration path for the PCA9556
I 8 general purpose input/output expander/collector
I Input/output configuration register
I Active HIGH polarity inversion register
I I²C-bus and SMBus interface logic
I Internal power-on reset
I Noise filter on SCL/SDA inputs
I Active LOW reset input
I 3 address pins allowing up to 8 devices on the I²C-bus/SMBus
I High-impedance open-drain on IO0
I No glitch on power-up
I Power-up with all channels configured as inputs
I Low standby current
I Operating power supply voltage range of 2.3 V to 5.5 V
I 5 V tolerant inputs/outputs
I 0 kHz to 400 kHz clock frequency
I ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Three packages offered: SO16, TSSOP16, HVQFN16