PCA9549 Datasheet, PDF (1/25 Pages) NXP Semiconductors – Octal bus switch with individually I2C-bus controlled enables

PCA9549
Octal bus switch with individually I²C-bus controlled enables
Rev. 02 — 13 July 2009
Product data sheet
1. General description
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled
by the I²C-bus. The low ON-state resistance of the switch allows connections to be made
with minimal propagation delay. Any individual A to B channel or combination of channels
can be selected via the I²C-bus, determined by the contents of the programmable Control
register. When the I²C-bus bit is HIGH (logic 1), the switch is on and data can flow from
Port A to Port B, or vice versa. When the I²C-bus bit is LOW (logic 0), the switch is open,
creating a high-impedance state between the two ports, which stops the data flow.
An active LOW reset input (RESET) allows the PCA9549 to recover from a situation
where the I²C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I²C-bus
state machine and causes all the bits to be open, as does the internal power-on reset
function.
Three address pins allow up to eight devices on the same bus.
2. Features
I 8-bit bus switch (CBT)
I 5 Ω switch connection between two ports
I I²C-bus interface logic; compatible with SMBus standards
I Active LOW RESET input
I 3 address pins allowing up to 8 devices on the I²C-bus
I Bit selection via I²C-bus, in any combination
I Power-up with all bits deselected
I Low R_on switches
I No glitch on power-up
I Supports hot insertion
I Low standby current
I Operating power supply voltage range of 2.3 V to 5.5 V
I 5 V tolerant inputs
I 0 Hz to 400 kHz clock frequency
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: SO24, TSSOP24, HVQFN24