PCA9548A Datasheet, PDF (1/26 Pages) NXP Semiconductors – 8-channel I2C switch with reset

PCA9548A
8-channel I²C-bus switch with reset
Rev. 03 — 7 July 2009
Product data sheet
1. General description
The PCA9548A is an octal bidirectional translating switch controlled via the I²C-bus. The
SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individual
SCx/SDx channel or combination of channels can be selected, determined by the
contents of the programmable control register.
An active LOW reset input allows the PCA9548A to recover from a situation where one of
the downstream I²C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the
I²C-bus state machine and causes all the channels to be deselected as does the internal
Power-on reset function.
The pass gates of the switches are constructed such that the V_DD pin can be used to limit
the maximum high voltage which will be passed by the PCA9548A. This allows the use of
different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features
I 1-of-8 bidirectional translating switches
I I²C-bus interface logic; compatible with SMBus standards
I Active LOW reset input
I 3 address pins allowing up to 8 devices on the I²C-bus
I Channel selection via I²C-bus, in any combination
I Power-up with all switch channels deselected
I Low R_on switches
I Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
I No glitch on power-up
I Supports hot insertion
I Low standby current
I Operating power supply voltage range of 2.3 V to 5.5 V
I 5 V tolerant inputs
I 0 Hz to 400 kHz clock frequency
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Three packages offered: SO24, TSSOP24, and HVQFN24