PCA9512A Datasheet, PDF (1/23 Pages) List of Unclassifed Manufacturers – Level shifting hot swappable I2C-bus and SMBus bus buffer

PCA9512A
Level shifting hot swappable I²C-bus and SMBus bus buffer
Rev. 04 — 19 August 2009
Product data sheet
1. General description
The PCA9512A is a hot swappable I²C-bus and SMBus buffer that allows I/O card
insertion into a live backplane without corruption of the data and clock buses and includes
two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems
while maintaining the best noise margin for each voltage level. Either pin may be powered
with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply
voltage is higher. Control circuitry prevents the backplane from being connected to the
card until a stop bit or bus idle occurs on the backplane without bus contention on the
card. When the connection is made, the PCA9512A provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
The PCA9512A rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9512A incorporates a digital
input pin that enables and disables the rise time accelerators on all four SDAn and SCLn
pins.
During insertion, the PCA9512A SDAn and SCLn pins are precharged to 1 V to minimize
the current required to charge the parasitic capacitance of the chip.
The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to
be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and
to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot connect to the
static offset I/Os used on the PCA9515/15A/16/16A/18, PCA9517 B side, or
P82B96 Sx/y side.
2. Features
I Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and
SCL corruption during live board insertion and removal from multipoint backplane
systems
I Compatible with I²C-bus Standard mode, I²C-bus Fast mode, and SMBus standards
I Built-in ∆V/∆t rise time accelerators on all SDA and SCL lines (0.6 V threshold) with
ability to disable ∆V/∆t rise time accelerator through the ACC pin for lightly loaded
systems, requires the bus pull-up voltage and respective supply voltage (V_CC or V_CC2)
to be the same
I 5 V to 3.3 V level translation with optimum noise margin
I High-impedance SDAn and SCLn pins for V_CC or V_CC2 = 0 V
I 1 V precharge on all SDAn and SCLn pins
I Supports clock stretching and multiple master arbitration and synchronization
I Operating power supply voltage range: 2.7 V to 5.5 V
I 0 Hz to 400 kHz clock frequency