PCA9509 Datasheet, PDF (1/19 Pages) NXP Semiconductors – Level translating I2C-bus/SMBus repeater

PCA9509
Level translating I²C-bus/SMBus repeater
Rev. 05 — 10 July 2009
Product data sheet
1. General description
The PCA9509 is a level translating I²C-bus/SMBus repeater that enables processor low
voltage 2-wire serial bus to interface with standard I²C-bus or SMBus I/O. While retaining
all the operating modes and features of the I²C-bus system during the level shifts, it also
permits extension of the I²C-bus by providing bidirectional buffering for both the data
(SDA) and the clock (SCL) lines, thus enabling the I²C-bus or SMBus maximum
capacitance of 400 pF on the higher voltage side. Port A allows a voltage range from
1.0 V (as low as 0.95 V in special cases) to V_CC(B) − 1.0 V and requires no external pull-up
resistors due to the internal current source. Port B allows a voltage range from 3.0 V to
5.5 V and is overvoltage tolerant. Both port A and port B SDA and SCL pins are
high-impedance when the PCA9509 is unpowered.
The bus port B drivers are compliant with SMBus I/O levels, while port A uses a current
sensing mechanism to detect the input or output LOW signal which prevents bus lock-up.
Port A uses a 1 mA current source for pull-up and a 200 Ω pull-down driver. This results in
a LOW on the port A accommodating smaller voltage swings. The output pull-down on the
port A internal buffer LOW is set for approximately 0.2 V, while the input threshold of the
internal buffer is set about 50 mV lower than that of the output voltage LOW. When the
port A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This
prevents a lock-up condition from occurring. The output pull-down on the port B drives a
hard LOW and the input level is set at 0.3 of SMBus or I²C-bus voltage level which
enables port B to connect to any other I²C-bus devices or buffer.
The PCA9509 drivers are not enabled unless V_CC(A) is above 0.8 V and V_CC(B) is above
2.5 V. The enable (EN) pin can also be used to turn the drivers on and off under system
control. Caution should be observed to only change the state of the EN pin when the bus
is idle.
2. Features
I Bidirectional buffer isolates capacitance and allows 400 pF on port B of the device
I Voltage level translation from port A (1 V [0.95 V in special cases] to V_CC(B) − 1.0 V) to
port B (3.0 V to 5.5 V)
I Requires no external pull-up resistors on lower voltage port A
I Active HIGH repeater enable input
I Open-drain inputs/outputs
I Lock-up free operation
I Supports arbitration and clock stretching across the repeater
I Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple masters
I Powered-off high-impedance I²C-bus pins