P89LPC9321 Datasheet, PDF(1/70 Page) NXP Semiconductors – 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

P89LPC9321 Datasheet, PDF (1/70 Pages) NXP Semiconductors – 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

P89LPC9321

8-bit microcontroller with accelerated two-clock 80C51 core

8 kB 3 V byte-erasable ï¬ash with 512-byte data EEPROM

Rev. 01 â 9 December 2008

Product data sheet

1. General description

The P89LPC9321 is a single-chip microcontroller, available in low cost packages, based

on a high performance processor architecture that executes instructions in two to four

clocks, six times the rate of standard 80C51 devices. Many system-level functions have

been incorporated into the P89LPC9321 in order to reduce component count, board

space, and system cost.

2. Features

2.1 Principal features

I 8 kB byte-erasable ï¬ash code memory organized into 1 kB sectors and 64-byte pages.

Single-byte erasing allows any byte(s) to be used as non-volatile data storage.

I 256-byte RAM data memory and a 512-byte auxiliary on-chip RAM.

I 512-byte customer data EEPROM on-chip allows serialization of devices, storage of

setup parameters, etc.

I Two analog comparators with selectable inputs and reference source.

I Single Programmable Gain Ampliï¬er (PGA) with selectable gains of 2x, 4x, 8x, or 16x

can be applied to analog comparator inputs.

I Two 16-bit counter/timers (each may be conï¬gured to toggle a port output upon timer

overï¬ow or to become a PWM output).

I A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit

prescaler and a programmable and readable 16-bit timer.

I Enhanced UART with a fractional baud rate generator, break detect, framing error

detection, and automatic address detection; 400 kHz byte-wide I2C-bus

communication port and SPI communication port.

I Capture/Compare Unit (CCU) provides PWM, input capture, and output compare

functions.

I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or

driven to 5.5 V).

I 4-level low voltage (brownout) detect allows a graceful system shutdown when power

fails. May optionally be conï¬gured as an interrupt.

I 28-pin TSSOP, PLCC and DIP packages with 23 I/O pins minimum and up to 26 I/O

pins while using on-chip oscillator and reset options.

▷