LPC81XM Datasheet, PDF (1/67 Pages) NXP Semiconductors – 32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and 4 kB SRAM

1.
LPC81xM _General
DRAFT
32-bit ARM Cortex-M0+ microcontroller; up
4 kB SRAM
Rev. 1.0 — 7 November 2012
description
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The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory
and 4 kB of SRAM.
The peripheral complement of the LPC81xM includes a CRC engine, one I²C-bus
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up
timer, and state-configurable timer, one comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O
pins.
2. Features and benefits
 System:
 ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with
single-cycle multiplier and fast single-cycle I/O port.
 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
 System tick timer.
 Serial Wire Debug (SWD) and JTAG boundary scan modes supported.
 Micro Trace Buffer (MTB) supported.
 Memory:
 16 kB on-chip flash programming memory with 64 Byte page write and erase.
 4 kB SRAM.
 ROM API support:
 Boot loader.
 USART drivers.
 I2C drivers.
 Power profiles.
 Flash In-Application Programming (IAP) and In-System Programming (ISP).
 Digital peripherals:
 High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18
General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
 GPIO interrupt generation capability with boolean pattern-matching feature on eight
GPIO inputs.
 Switch matrix for flexible configuration of each I/O pin function.
 State Configurable Timer (SCT) with input and output functions (including capture
and match) assigned to pins through the switch matrix.