LPC2917 Datasheet, PDF (1/86 Pages) NXP Semiconductors – ARM9 microcontroller with CAN and LIN

LPC2917/2919/01
ARM9 microcontroller with CAN and LIN
Rev. 02 — 17 June 2009
Preliminary data sheet
1. General description
The LPC2917/2919/01 combine an ARM968E-S CPU core with two integrated TCM
blocks operating at frequencies of up to 125 MHz, CAN and LIN, 56 kB SRAM, up to
768 kB flash memory, external memory interface, two 10-bit ADCs, and multiple serial and
parallel interfaces in a single chip targeted at consumer, industrial, medical, and
communication markets. To optimize system power consumption, the LPC2917/2919/01
has a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and
scaling.
2. Features
I ARM968E-S processor running at frequencies of up to 125 MHz maximum.
I Multi-layer AHB system bus at 125 MHz with three separate layers.
I On-chip memory:
N Two Tightly Coupled Memories (TCM), 16 kB Instruction TCM (ITCM), 16 kB Data
TCM (DTCM).
N Two separate internal Static RAM (SRAM) instances; 32 kB SRAM and 16 kB
SRAM.
N 8 kB ETB SRAM also available for code execution and data.
N Up to 768 kB high-speed flash-program memory.
N 16 kB true EEPROM, byte-erasable and programmable.
I Dual-master, eight-channel GPDMA controller on the AHB multi-layer matrix which can
be used with the SPI interfaces and the UARTs, as well as for memory-to-memory
transfers including the TCM memories.
I External Static Memory Controller (SMC) with eight memory banks; up to 32-bit data
bus; up to 24-bit address bus.
I Serial interfaces:
N Two-channel CAN controller supporting FullCAN and extensive message filtering
N Two LIN master controllers with full hardware support for LIN communication. The
LIN interface can be configured as UART to provide two additional UART
interfaces.
N Two 550 UARTs with 16-byte Tx and Rx FIFO depths, DMA support, and
RS485/EIA-485 (9 bit) support.
N Three full-duplex Q-SPIs with four slave-select lines; 16 bits wide; 8 locations deep;
Tx FIFO and Rx FIFO.
N Two I²C-bus interfaces.