LPC2364_10 Datasheet, PDF (1/59 Pages) NXP Semiconductors – Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC

LPC2364/65/66/67/68
Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash
with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC
Rev. 06 — 1 February 2010
Product data sheet
1. General description
The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S
CPU with real-time emulation that combines the microcontroller with up to 512 kB of
embedded high-speed flash memory. A 128-bit wide memory interface and a unique
accelerator architecture enable 32-bit code execution at the maximum clock rate. For
critical performance in interrupt service routines and DSP algorithms, this increases
performance up to 30 % over Thumb mode. For critical code size applications, the
alternative 16-bit Thumb mode reduces code by more than 30 % with minimal
performance penalty.
The LPC2364/65/66/67/68 are ideal for multi-purpose serial communication applications.
They incorporate a 10/100 Ethernet Media Access Controller (MAC), USB full speed
device with 4 kB of endpoint RAM (LPC2364/66/68 only), four UARTs, two CAN channels
(LPC2364/66/68 only), an SPI interface, two Synchronous Serial Ports (SSP), three I²C
interfaces, and an I²S interface. This blend of serial communications interfaces combined
with an on-chip 4 MHz internal oscillator, SRAM of up to 32 kB, 16 kB SRAM for Ethernet,
8 kB SRAM for USB and general purpose use, together with 2 kB battery powered SRAM
make these devices very well suited for communication gateways and protocol
converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, one PWM unit, a
CAN control unit (LPC2364/66/68 only), and up to 70 fast GPIO lines with up to 12 edge
or level sensitive external interrupt pins make these microcontrollers particularly suitable
for industrial control and medical systems.
2. Features
„ ARM7TDMI-S processor, running at up to 72 MHz
„ Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. Flash program memory is on the ARM
local bus for high performance CPU access.
„ 8 kB/32 kB of SRAM on the ARM local bus for high performance CPU access.
„ 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM.
„ 8 kB SRAM for general purpose DMA use also accessible by the USB.
„ Dual Advanced High-performance Bus (AHB) system that provides for simultaneous
Ethernet DMA, USB DMA, and program execution from on-chip flash with no
contention between those functions. A bus bridge allows the Ethernet DMA to access
the other AHB subsystem.
„ Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
„ General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP
serial interfaces, the I²S port, and the Secure Digital/MultiMediaCard (SD/MMC) card
port, as well as for memory-to-memory transfers.